The present invention relates to an arithmetic processor and, more particularly, to a high speed arithmetic processor utilizing addition, subtraction and sign inversion for performing arithmetic operations, which may be implemented by LSI.
A high speed multiplier is discussed on pp. 683 to 690 of Trans. of IECE Japan, Vol. J66-D, No. 6 (1983). A high speed divider is discussed on pp. 450 to 457 of Trans. of IECE Japan, Vol. J67-D, No. 4 (1984). These arithmetic units execute multiplication or division by means of combinational circuitry using a redundant binary expression (i.e., a kind of signed digit ("SD") expression) in which each digit is represented by a set of elements {-1, 0, 1}.
For example, a prior art divider is implemented by combinational circuitry using ECL (Emitter-Coupled-Logic) 4-input NOR/OR gates based on shift, subtract, restore division using the redundant binary expression. While that prior art divider has faster arithmetic processing speeds and has a regular array structure, no consideration has been given to factors such as a reduction in the number of transistors required and implementation by other circuitry (e.g., CMOS).
Dividers in wide use today are sequential circuits each having a subtracter (adder) and a shifter. However, it is well known that as the number of digits of the operands increases, an exceedingly long time is required for those dividers to perform arithmetic operations. On the other hand, large-size computers having high-speed multipliers often employ multiplication-type division in which division is performed by repetition of multiplication. However, implementation of such multiplication type division by combinational circuitry requires large numbers of hardware elements, and is therefore impractical.
With respect specifically to a high-speed arithmetic unit employing signed digit numbers for arithmetic operations, it has been proposed to carry out an arithmetic operation such as multiplication or division with combinational circuitry by utilizing an ECL logic element that enables NOR and OR operations to be simultaneously performed. However, little consideration has been given to reducing the number of transistors required, to implementation of that unit using other types of circuitry, and to differences in the arithmetic operation times (i.e., the number of transistor gates in the computing path) of the multiplier, divider or an ALU, and, therefore, the following problems are associated with that high-speed arithmetic unit:
(1) as the number of digits of the operands increases, the number of gates required increases which makes it difficult to fabricate a multiplier and an ALU on a single VLSI chip;
(2) if the subtracter, the ALU and the multiplier of the arithmetic processor utilize a number of common clocks, processing time for addition/subtraction or multiplication is increased.